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| MPR604HSU-02 (IBM Order Number) MPC604EC/D (Motorola Order Number) 11/95 REV 1 TM Advance Information PowerPC 604TM RISC Microprocessor Hardware Specifications The PowerPC 604 microprocessor is an implementation of the PowerPCTM family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical characteristics of the 604. For information about the functionality of the 604, refer to the PowerPC 604 RISC Microprocessor Users Manual. This document contains the following topics: Topic Page In this document, the term "604" is used as an abbreviation for the phrase "PowerPC 604 microprocessor." The PowerPC 604 microprocessors are available from IBM as PPC604 and from Motorola as MPC604. The PowerPC name, the PowerPC logotype, and PowerPC 604 are trademarks of International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. (c) Motorola Inc. 1995 Portions hereof (c) International Business Machines Corp. 1991-1995. All rights reserved. 604 Hardware Specifications Section 1.1, "General Parameters" Section 1.2, "Electrical and Thermal Characteristics" Section 1.3, "AC Electrical Characteristics" Section 1.4, "PowerPC 604 Microprocessor Pin Assignments" Section 1.5, "PowerPC 604 Microprocessor Pinout Listings" Section 1.6, "PowerPC 604 Microprocessor Package Description" Section 1.7, "System Design Information" Section 1.8, "Thermal Management Information" Section 1.9, "Ordering Information" 2 2 3 11 14 19 25 27 30 1.1 General Parameters 0.5 m CMOS, four-layer metal 196 mm2, 12.4 mm x 15.8 mm Surface-mount 304-pin C4-CQFP Surface-mount 255-lead ceramic ball grid array (BGA) Voltage 3.3 V 5% Maximum power dissipation 24 W @ 133 MHz 19 W @ 100 MHz Technology Chip size Packages 1.2 Electrical and Thermal Characteristics This section provides both the AC and DC electrical specifications and thermal characteristics for the 604. The following specifications are preliminary and subject to change without notice. For the most recent specifications, contact your local Motorola or IBM sales office. 1.2.1 DC Electrical Characteristics Table 1 and Table 2 provide the absolute maximum rating and thermal characteristics for the 604. Table 1. PowerPC 604 Microprocessor Absolute Maximum Ratings Characteristic Supply voltage Input voltage Storage temperature range Symbol Vdd Vin Tstg Value -0.3 to 3.6 -0.3 to 5.5 -55 to 150 Unit V V C Notes: 1. Functional operating conditions are given in DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Input voltage must not be greater than the supply voltage by more than 2.5 V during power-on reset. Table 2. PowerPC 604 Microprocessor Thermal Characteristics Characteristic C4-CQFP package thermal resistance, junction-to-case BGA package thermal resistance, junction-to-case Symbol JC JC Value 0.03 0.03 Rating C/W C/W Notes: 1. For the BGA package, the JC measurement is made from die junction to the back of the bare silicon die. 2. The junction temperature of the chip is a function of several parameters including JC. Please refer to Section 1.8, "Thermal Management Information," for additional details. 2 Preliminary/Subject to Change without Notice 604 Hardware Specifications Table 3 provides the DC electrical characteristics for the 604. Table 3. PowerPC 604 Microprocessor DC Electrical Specifications Vdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C, Input capacitance = 10 pF maximum Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Output high voltage, IOH = -9 mA Output low voltage, IOL = 9 mA Symbol VIH VIL CVIH CVIL VOH VOL 2 0 2.4 0 2.4 -- Min Max 5.5 0.8 5.5 0.4 -- 0.4 Unit V V V V V V Table 4 provides the power dissipation numbers for the 604. Table 4. PowerPC 604 Microprocessor Power Dissipation Processor Core Frequency Unit 100 MHz Full-On Mode Typical Maximum 14.5 19.0 17.0 22.5 18.5 24.0 W W 120 MHz 133 MHz 1 2 3 Notes Notes: 1. Power measured does not include power dissipated in output drivers. 2. Typical power is an average value measured at 3.3 V in a system executing typical applications and benchmark sequences. Typical power numbers should be used in planning for proper thermal management. 3. Maximum power is measured at 3.3 V using a worst case instruction mix. These values should be used for power supply design. 1.3 AC Electrical Characteristics This section provides the AC electrical characteristics for the 604. These specifications are for parts that operate at processor core frequencies of 100, 120, and 133 MHz. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG0-PLL_CFG3 pins. All timings are specified respective to the SYSCLK. 604 Hardware Specifications Preliminary/Subject to Change without Notice 3 1.3.1 Clock AC Specifications Table 5 provides the clock AC timing specifications as defined in Figure 1. Table 5. PowerPC 604 Microprocessor Clock AC Timing Specifications Vdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C 100 MHz Num Characteristic Min Frequency of operation Frequency of VCO SYSCLK frequency 1 2,3 4 5 6 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at 1.4 V SYSCLK jitter Internal PLL relock time 50 180 16.67 15.0 1.0 40 -- -- Max 100.0 360 66.67 60.0 2.0 60 150 100 Min 60.0 180 20.0 15.0 1.0 40 -- -- Max 120.0 360 66.67 50.0 2.0 60 150 100 Min 66.67 180 22.2 15.0 1.0 40 -- -- Max 133.3 360 66.67 45.0 2.0 60 150 100 MHz MHz MHz ns ns % ps s 5 6, 7 4 1 2 3 120 MHz 133 MHz Unit Notes Notes: 1. Times shown in specifications are only valid for the range of processor core frequencies specified. 2. Caution: The SYSCLK frequency and PLL_CFG0-PLL_CFG3 settings must be chosen such that the resulting CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 3. AC timing specifications are tested up to the maximum SYSCLK (bus) frequency shown in Table 5. However, it is theoretically possible to attain higher SYSCLK frequencies if allowed for by system design. 4. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 5. This number refers to cycle-to-cycle jitter. 6. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time (100 s) during the power-on reset sequence. 7. Relock timing is guaranteed by design and is not tested. Figure 1 provides the SYSCLK input timing diagram. 1 4 2 CVih SYSCLK VM CVil VM = Midpoint Voltage (1.4 V) Figure 1. SYSCLK Input Timing Diagram 3 4 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.3.2 Input AC Specifications Table 6 provides the input AC timing specifications for the 604 as defined in Figure 2. Table 6. PowerPC 604 Microprocessor Input AC Timing Specifications Vdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C 100 MHz Num Characteristic Min 7 ARTRY, SHD, ABB, TS, XATS, AACK,BG, DRTRY, TA, DBG, DBB, TEA, DBDIS, and DBWO valid to SYSCLK (setup) All other inputs valid to SYSCLK (setup) SYSCLK to all inputs invalid (hold) Mode select input valid to HRESET (input setup for DRTRY) HRESET to mode select input invalid (input hold for DRTRY) 5.5 Max -- 120 MHz Min 5.0 Max -- 133 MHz Unit Min 5.0 Max ns Notes 8 9 10 11 5.5 0 8* tsysclk 0 -- -- -- -- 4.0 0 8* tsysclk 0 -- -- -- -- 4.0 0 8* tsysclk 0 -- -- -- -- ns ns ns ns 1 1 2,3,4,5 2,3,4,5 Notes: 1. All other input signals include the following signals--all inputs except ARTRY, SHD, ABB, TS, XATS, AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs. 2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). 3. tsysclk is the period of the external clock (SYSCLK) in nanoseconds. 4. These values are guaranteed by design, and are not tested. 5. Note this is for configuration of the fast-L2 mode. The DRTRY signal must be held negated during fast-L2 mode. Figure 2 provides the input timing diagram for the 604. VM SYSCLK 7 8 9 ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 2. PowerPC 604 Microprocessor Input Timing Diagram 604 Hardware Specifications Preliminary/Subject to Change without Notice 5 Figure 3 provides the timing diagram for the fast-L2 mode select input. HRESET VM 10 11 FAST-L2 MODE PIN VM = Midpoint Voltage (1.4V) Figure 3. Fast-L2 Mode Select Input Timing Diagram 1.3.3 Output AC Specifications Table 7 provides the output AC timing specifications for the 604 (shown in Figure 4). Table 7. PowerPC 604 Microprocessor Output AC Timing Specifications Vdd = 3.3 5% V dc, GND = 0 V dc, CL = 50 pF, 0 Tj 105 C 100 MHz Num Characteristic Min 12 13a SYSCLK to output driven (output enable time) SYSCLK to TS, XATS, ARTRY, SHD, ABB, and DBB output valid (for 5.5 V to 0.8 V) SYSCLK to TS, XATS, ARTRY, SHD, ABB, and DBB output valid (for 3.6 V to 0.8 V) SYSCLK to all other signals output valid (for 5.5 V to 0.8 V) SYSCLK to all other signals output valid (for 3.6 V to 0.8 V) SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) SYSCLK to output high impedance TS, XATS SYSCLK to ABB and DBB high impedance after precharge SYSCLK to ARTRY and SHD high impedance before precharge 0.75 -- Max -- 8.5 Min 0.75 -- Max -- 7.5 Min 0.75 -- Max -- 7.0 ns ns 1 2 120 MHz 133 MHz Unit Notes 13b -- 7.5 -- 6.5 -- 6.0 ns 14a 14b 15 16 -- -- 1.0 -- 8.5 7.5 -- 7.0 -- -- 1.0 -- 7.5 6.5 -- 6.5 -- -- 1.0 -- 7.0 6.0 -- 6.0 ns ns ns ns 2 17 18 19 -- -- -- 7.0 1.0* tsysclk 7.0 -- -- -- 6.5 1.0* tsysclk 6.5 -- -- -- 6.0 1.0* tsysclk 6.0 ns ns ns 3 6 Preliminary/Subject to Change without Notice 604 Hardware Specifications Table 7. PowerPC 604 Microprocessor Output AC Timing Specifications (Continued) Vdd = 3.3 5% V dc, GND = 0 V dc, CL = 50 pF, 0 Tj 105 C 100 MHz Num Characteristic Min 20 SYSCLK to ARTRY and SHD precharge enable -- Max 0.5* tsysclk + 0.75 1.5* tsysclk 2.0* tsysclk Min -- Max 0.5* tsysclk + 0.75 1.5* tsysclk 2.0* tsysclk Min -- Max 0.5* tsysclk + 0.75 1.5* tsysclk 2.0* tsysclk ns 3 120 MHz 133 MHz Unit Notes 21 22 Maximum delay to ARTRY and SHD precharge SYSCLK to ARTRY and SHD high impedance after precharge Rise time (ARTRY, SHD, ABB, DBB, TS, and XATS) Rise time (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) Fall time (ARTRY, SHD, ABB, DBB, TS, and XATS) Fall time (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) -- -- 1.0 1.0 1.0 1.0 -- -- 1.0 1.0 1.0 1.0 -- -- 1.0 1.0 1.0 1.0 ns ns ns ns ns ns 3 3 4 4 4 4 Notes: 1. These values are guaranteed by design, and are not tested. 2. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from 3.6 V to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels). 3. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 4. These specifications are nominal values. 604 Hardware Specifications Preliminary/Subject to Change without Notice 7 Figure 4 provides the output timing diagram for the 604. VM VM 14 15 VM SYSCLK All Outputs (Except TS, ABB, DBB, ARTRY, XATS, SHD) 12 16 13 13 15 17 TS, XATS 18 ABB, DBB 22 21 20 ARTRY, SHD 19 Notes: VM = Midpoint voltage (1.4 V) All output specifications are measured from 0.8 V or 2.0 V of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Figure 4. PowerPC 604 Microprocessor Output Timing Diagram The output specifications of the 604 for both driving high and driving low depend on the capacitive loading on each output and the drive capability enabled for that output. Additionally, the timing specifications for outputs driving low also depend on the voltage swing required to drive to 0.8 V (either 5.5 V to 0.8 V or 3.6 V to 0.8 V). Table 7 provides the output AC timing specifications for a 50 pF load. In order to derive the actual timing specifications for a given set of conditions, it is recommended that IBIS simulation models be used. Contact the local Motorola or IBM sales office for information on the availability of these models. 8 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.3.4 JTAG AC Timing Specifications Table 8 provides the JTAG AC timing specifications. Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) Num Characteristic TCK frequency of operation 1 2 3 4 5 6 7 8 9 10 11 12 13 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time TCK to output data valid TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance 0 62.5 25 0 13 40 0 27 4 3 0 25 4 3 Min Max 16 -- -- 3 -- -- -- -- 35 24 -- -- 24 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 Notes Notes: 1. Load capacitance = 50 pF. 2. TRST is an asynchronous signal. The setup time is for test purposes. Figure 5 provides the JTAG clock input timing diagram. 1 TCK 2 2 VM 3 3 VM Figure 5. Clock Input Timing Diagram 604 Hardware Specifications Preliminary/Subject to Change without Notice 9 Figure 6 provides the TRST timing diagram. TCK 4 TRST 5 Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. VIH 6 DATA INPUTS 8 DATA OUTPUTS 9 DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID OUTPUT DATA VALID 7 TCK VIL INPUT DATA VALID Figure 7. Boundary-Scan Timing Diagram 10 Preliminary/Subject to Change without Notice 604 Hardware Specifications Figure 8 provides the test access port timing diagram. TCLK TCLK VIL 10 VIH 11 TDI, TMS TDI, TMS INPUT DATAVALID INPUT DATA VALID 12 TDOTDO OUTPUT DATA VALID OUTPUT DATA VALID 13 TDO TDO 12 TDO TDO OUTPUT DATA VALID OUTPUT DATA VALID Figure 8. Test Access Port Timing Diagram 1.4 PowerPC 604 Microprocessor Pin Assignments The following sections contain the pinout diagrams for the 604. Note that the 604 is currently offered in two packages. Motorola and IBM both offer a C4 Ceramic Quad Flat Pack (C4-CQFP), and a Ball Grid Array (BGA) package. Both IBM and Motorola C4-CQFP and BGA packages have identical pinouts. 604 Hardware Specifications Preliminary/Subject to Change without Notice 11 1.4.1 Pinout Diagram for the C4-CQFP Package Figure 9 contains the pinout diagram of the C4-CQFP package for the 604. VDD TT 4 OGND A0 GND A2 OVDD A4 VDD A6 OGND A8 GND A 10 OVDD A 12 VDD A 14 OGND A 16 GND A 18 OVDD A 20 VDD A 22 OGND A 24 GND A 26 OVDD DRTRY VDD TA TEA DBDIS GND A 28 OGND XATS VDD TS OVDD GND DBB OGND A 30 VDD DL 0 OVDD DL 1 GND DL 2 OGND DL 3 VDD DL 4 OVDD DL 5 GND DL 6 OGND DL 7 VDD DL 8 OVDD DL 9 GND DL 10 OGND DL 11 VDD DL 12 OVDD DL 13 GND 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 TT 3 OVDD TT 2 MCP SMI INT OGND SRESET OVDD TT 1 TT 0 OGND TBST VDD TSIZ 2 OVDD TSIZ 1 TSIZ 0 OGND TDO OVDD TDI TMS TCK TRST L2_TSTCLK L1_ TSTCLK LSSD_MODE GND VDD PLL_CFG 3 AVDD PLL_CFG 2 PLL_CFG 1 SYSCLK PLL_CFG 0 HRESET CKSTP_IN CKSTP_OUT OGND HALTED RUN ARRAY_WR OVDD L2_INT DPE OGND APE OVDD BR OGND CLK_OUT TC 2 OVDD TC 1 OGND TC 0 OVDD CSE 1 CSE 0 OGND AP 3 GND AP 2 OVDD AP 1 AP 0 OGND RSRV OVDD TBEN DRVMOD 1 DRVMOD 0 WT OVDD CI 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 TOP VIEW 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 DL 14 OGND DL 15 OVDD DL 16 DH 0 OGND DH 1 OVDD DH 2 DH 3 OGND DH 4 OVDD DH 5 OGND DL 17 DL 18 OVDD DL 19 OGND DL 20 OVDD DL 21 DL 22 OGND DH 6 OVDD DH 7 OGND DH 8 DH 9 OVDD DH 10 OGND DH 11 OVDD DH 12 DH 13 OGND DH 14 OVDD DH 15 OGND DH 16 DH 17 OVDD DH 18 OGND DH 19 OVDD DH 20 DH 21 OGND DH 22 OVDD DH 23 OGND DH 24 DH 25 OVDD DH 26 OGND DH 27 OVDD DH 28 DH 29 OGND DH 30 OVDD DH 31 DL 31 OVDD DL 30 OGND DL 29 12 Preliminary/Subject to Change without Notice VDD GBL OGND A1 GND A3 OVDD A5 VDD A7 OGND A9 GND A 11 OVDD A 13 VDD A 15 OGND A 17 GND A 19 OVDD A 21 VDD A 23 OGND A 25 GND A 27 OVDD DBWO VDD DBG BG AACK GND A 29 OGND SHD VDD ARTRY OVDD GND ABB OGND A 31 VDD DP 0 OVDD DP 1 GND DP 2 OGND DP 3 VDD DP 4 OVDD DP 5 GND DP 6 OGND DP 7 VDD DL 23 OVDD DL 24 GND DL 25 OGND DL 26 VDD DL 27 OVDD DL 28 GND Figure 9. Pinout Diagram of the C4-CQFP Package 604 Hardware Specifications 1.4.2 Pinout Diagram for the BGA Package Figure 10 (in part A) shows the pinout of the BGA package as viewed from the top surface. Part B shows the side profile of the BGA package to indicate the direction of the top surface view. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T Not to Scale Part B Substrate Asm. Encapsulation View Die Figure 10. Pinout of the BGA Package as Viewed from the Top Surface 604 Hardware Specifications Preliminary/Subject to Change without Notice 13 1.5 PowerPC 604 Microprocessor Pinout Listings The following sections contain the pinout listings for the 604 C4-CQFP and BGA packages. 1.5.1 Pinout Listing for the C4-CQFP Package Table 9 provides the pinout listing for the 604 C4-CQFP package. Table 9. Pinout Listing for the C4-CQFP Package Signal Name A0-A31 Pin Number 225, 4, 223, 6, 221, 8, 219, 10, 217, 12, 215, 14, 213, 16, 211, 18, 209, 20, 207, 22, 205, 24, 203, 26, 201, 28, 199, 30, 191, 38, 182, 47 36 45 295, 294, 292, 290 276 271 42 260 35 278 304 266 267 280 288, 287 184 34 193 32 147, 145, 143, 142, 140, 138, 126, 124, 122, 121, 119, 117, 115, 114, 112, 110, 108, 107, 105, 103, 101, 100, 98, 96, 94, 93, 91, 89, 87, 86, 84, 82 180, 178, 176, 174, 172, 170, 168, 166, 164, 162, 160, 158, 156, 154, 152, 150, 148, 136, 135, 133, 131, 129, 128, 65, 67, 69, 71, 73, 75, 77, 79, 81 49, 51, 53, 55, 57, 59, 61, 63 Active High I/O I/O AACK ABB AP0-AP3 APE ARRAY_WR1 ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE0-CSE1 DBB DBG DBDIS DBWO DH0-31 Low Low High Low Low Low -- Low Low Low Low Low -- High Low Low Low Low High Input I/O I/O Output Input I/O -- Input Output Output Input Output Output Output I/O Input Input Input I/O DL0-DL31 High I/O DP0-DP7 High I/O 14 Preliminary/Subject to Change without Notice 604 Hardware Specifications Table 9. Pinout Listing for the C4-CQFP Package (Continued) Signal Name DPE DRTRY DRVMOD0-DRVMOD1 2 GBL GND 274 197 301, 300 2 5, 13, 21, 29, 37, 44, 52, 60, 68, 76, 153, 161, 169, 177, 185, 192, 200, 208, 216, 224, 257, 291 269 265 234 255 273 254 256 232 3, 11, 19, 27, 39, 46, 54, 62, 70, 78, 85, 90, 95, 99, 104, 109, 113, 118, 123, 127, 132, 137, 141, 146, 151, 159, 167, 175, 183, 190, 202, 210, 218, 226, 235, 240, 247, 268, 275, 279, 284, 289, 296 7, 15, 23, 31, 43, 50, 58, 66, 74, 80, 83, 88, 92, 97, 102, 106, 111, 116, 120, 125, 130, 134, 139, 144, 149, 155, 163, 171, 179, 186, 198, 206, 214, 222, 230, 237, 244, 249, 272, 277, 282, 286, 293, 298, 303 264, 262, 261, 259 297 270 40 233 236 263 195 299 241 285, 283, 281 Pin Number Active Low Low High Low -- I/O Output Input Input I/O -- HALTED HRESET INT L1_TSTCLK 1 L2_INT L2_TSTCLK 1 LSSD_MODE 1 MCP OGND High Low Low Low High Low Low Low -- Output Input Input Input Input Input Input Input -- OVDD 3 -- -- PLL_CFG0-PLL_CFG3 RSRV RUN SHD SMI SRESET SYSCLK TA TBEN TBST TC0-TC2 High Low High Low Low Low -- Low High Low High Input Output Input I/O Input Input Input Input Input I/O Output 604 Hardware Specifications Preliminary/Subject to Change without Notice 15 Table 9. Pinout Listing for the C4-CQFP Package (Continued) Signal Name TCK TDI TDO TEA TMS TRST TS TSIZ0-TSIZ2 TT0-TT4 WT VDD 3 252 250 248 194 251 253 187 246, 245, 243 239, 238, 231, 229, 227 302 1, 9, 17, 25, 33, 41, 48, 56, 64, 72, 157, 165, 173, 181, 188, 196, 204, 212, 220, 228, 242, 258 189 Pin Number Active High High High Low High Low Low High High Low -- I/O Input Input Output Input Input Input I/O I/O I/O Output -- XATS Low I/O Notes: 1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation. 2. These are drive mode signals that must be pulled up to VDD to operate in accordance with these specifications. 3. In the Motorola 604 C4-CQFP package, there is no electrical distinction between the OVDD and the VDD pins. These signals are internally shorted together. The OVDD and VDD signals have been listed separately to maintain compatibility with future parts. 1.5.2 Pinout Listing for the BGA Package Table 10 provides the pinout listing for the 604 BGA package. Table 10. Pinout Listing for the BGA Package Signal Name A0-A31 Pin Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04 1 Active High I/O I/O AACK ABB AP0-AP3 APE ARRAY_WR ARTRY AVDD Low Low High Low Low Low -- Input I/O I/O Output Input I/O -- B07 J04 A10 16 Preliminary/Subject to Change without Notice 604 Hardware Specifications Table 10. Pinout Listing for the BGA Package (Continued) Signal Name BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE0-CSE1 DBB DBG DBDIS DBWO DH0-31 L01 B06 E01 D08 A06 D07 B01, B05 J14 N01 H15 G04 P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 D05, C03 F01 C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 B08 A07 B15 1 Pin Number Active Low Low Low Low Low -- High Low Low Low Low High I/O Input Output Output Input Output Output Output I/O Input Input Input I/O DL0-DL31 High I/O DP0-DP7 DPE DRTRY DRVMOD0-DRVMOD1 2 GBL GND High Low Low High Low -- I/O Output Input Input I/O -- HALTED HRESET INT L1_TSTCLK L2_INT L2_TSTCLK 1 LSSD_MODE 1 MCP OVDD 3 High Low Low Low High Low Low Low -- Output Input Input Input Input Input Input Input -- D11 D06 D12 B10 C13 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 604 Hardware Specifications Preliminary/Subject to Change without Notice 17 Table 10. Pinout Listing for the BGA Package (Continued) Signal Name PLL_CFG0-PLL_CFG3 RSRV RUN SHD SMI SRESET SYSCLK TA TBEN TBST TC0-TC2 TCK TDI TDO TEA TMS TRST TS TSIZ0-TSIZ2 TT0-TT4 WT VDD 3 XATS A08, B09, A09, D09 D01 C08 H04 A16 B14 C09 H14 C02 A14 A02, A03, C06 C11 A11 A12 H13 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 J16 Pin Number Active High Low High Low Low Low -- Low High Low High High High High Low High Low Low High High Low -- Low I/O Input Output Input I/O Input Input Input Input Input I/O Output Input Input Output Input Input Input I/O I/O I/O Output -- I/O Notes: 1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation. 2. These are drive mode signals that must be pulled up to VDD to operate in accordance to these specifications. 3. In the 604 BGA package, there is no electrical distinction between the OVDD and the VDD pins. These signals are internally shorted together. The OVDD and VDD signals have been listed separately to maintain compatibility with future parts. 18 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.6 PowerPC 604 Microprocessor Package Description The following sections provide the package parameters and the mechanical dimensions for the 604. 1.6.1 C4-CQFP Package Description The following sections provide the package parameters and mechanical dimensions for the C4-CQFP package. 1.6.1.1 Motorola C4-CQFP Package Parameters The package parameters for the Motorola C4-CQFP are as provided in the following list. The package type is 40 mm, 304-pin ceramic quad flat pack. Package outline Interconnects Pitch Lead plating C4 encapsulation Maximum module height Co-planarity specification 40 mm 304 0.5 mm Ni Au Glass-filled Epoxy 3.25 mm 0.10 mm 1.6.1.2 IBM C4-CQFP Package Parameters The package parameters for the IBM C4-CQFP are as provided in the following list. The package type is 40 mm, 304-pin ceramic quad flat pack. Package outline Interconnects Pitch Lead plating Lead encapsulation C4 encapsulation Maximum module height Co-planarity specification 40 mm 304 0.5 mm Ni Au Glass-filled Epoxy Glass-filled Epoxy 2.92 mm 0.08 mm 604 Hardware Specifications Preliminary/Subject to Change without Notice 19 1.6.1.3 Mechanical Dimensions of the Motorola C4-CQFP Package Figure 11 shows the mechanical dimensions of the Motorola C4-CQFP package. 4X 76 TIPS 153 152 U 228 229 0.20 (0.008) T L-M N G P -X- X = L, M, N AC AC -L- F -M- BV VIEW Y 3 PLACES J V1 D 0.08 (0.003) M T L S -M S 304 1 76 77 SECTION AC-AC ROTATED 90 CW NOTES: 1. DIMENSIONS AND TOLERENCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE CERAMIC. 4. DATUMS -L- , -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H- . 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T- . -N- S1 3X VIEW Y A 0.20 (0.008) M H L S -M S N S S 0.20 (0.008) M H L S -M S N S C -H- -T- SEATING PLANE 0.10 (0.004) T VIEW AB C3 1 C6 (W) -H- DATUM PLANE R (R1) 0.25 (0.010) DIM A B C C1 C2 C3 C6 D E F G J K P R1 R2 S S1 U V V1 W Z 1 MILLIMETERS MIN MAX 39.55 39.75 39.55 39.75 2.50 3.25 0.50 -- 2.00 2.40 0.60 1.00 -- 0.50 0.18 0.30 0.50 0.70 5.00 16.00 0.50 BASIC 0.12 0.17 0.50 REF 0.25 BASIC 0.10 0.20 0.15 REF 42.60 BASIC 21.30 BASIC 5.00 16.00 42.60 BASIC 21.30 BASIC 0.63 REF 1.48 REF 1 7 2 6 INCHES MIN MAX 1.557 1.564 1.557 1.564 0.098 0.128 0.020 -- 0.079 0.094 0.024 0.039 -- 0.020 0.007 0.012 0.020 0.028 0.197 0.630 0.020 BASIC 0.005 0.007 0.020 REF 0.010 BASIC 0.004 0.008 0.006 REF 1.677 BASIC 0.839 BASIC 0.197 0.630 1.677 BASIC 0.839 BASIC 0.025 REF 0.058 REF 1 7 2 6 C2 C1 R (R2) (K) E (Z) VIEW AB Figure 11. Mechanical Dimensions of the Motorola C4-CQFP Package 20 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.6.1.4 Mechanical Dimensions of the IBM C4-CQFP Package Figure 12 shows the mechanical dimensions for the IBM C4-CQFP package. S A 228 229 VIEW Y (see Figure 13) 0.13 (0.005) M T L-M S N S 153 152 B V -L- -M- 304 1 76 77 -N- 0.13 (0.005) M T L - M S N S 0.20 (0.008) T L - M S N S 76 TIPS, 4 PLACES VIEW P (see Figure 14) W C -T- SEATING PLANE 0.08 (0.003) Figure 12. Mechanical Dimensions of the IBM C4-CQFP Package 604 Hardware Specifications Preliminary/Subject to Change without Notice 21 Figure 13 and Figure 14 provide a more detailed representation of portions of IBM C4-CQFP package. J1 (see Section J1-J1 below) J1 -X- X = L, M, or N 4 Places Section J1-J1 304 Places J Notes: D = Width J = Height D Figure 13. IBM C4-CQFP Mechanical Dimensions--View Y Ref A, B E Radius (0.25 max) 304X G 0.08 (0.003) M L-M S N S K Figure 14. IBM C4-CQFP Mechanical Dimensions--View P 22 Preliminary/Subject to Change without Notice 604 Hardware Specifications Table 11 lists the mechanical dimensions values for the IBM C4-CQFP package. Table 11. Mechanical Dimensions Values Dim A B C D E G J K S V W Millimeters Min 39.93 39.93 2.32 0.23 Max 40.08 40.08 2.92 0.28 0.635 REF 0.5 BSC 0.12 0.40 42.4 42.4 0.35 0.20 0.60 42.8 42.8 -- Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension--millimeter. 3. Datums - L -, -M -, and - N - to be determined at seating plane. 4. Dimensions S and V to be determined at seating plane - T-. 5. Dimensions A and B to outside of lead clip. 1.6.2 BGA Package Description The following sections provide the package parameters and mechanical dimensions for the IBM and Motorola BGA packages. 1.6.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 21 mm, 256-lead ceramic ball grid array (BGA). Package outline Interconnects Pitch Maximum module height 21 mm 255 1.27 mm 3.16 mm 604 Hardware Specifications Preliminary/Subject to Change without Notice 23 1.6.2.2 Mechanical Dimensions of the BGA Package Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the IBM and Motorola BGA package. 2X A1 CORNER 0.200 A -E- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 21.000 BSC 21.000 BSC 2.300 3.160 0.820 0.930 1.270 BSC 0.790 0.990 0.635 BSC 5.000 16.000 5.000 16.000 INCHES MIN MAX 0.827 BSC 0.827 BSC 0.091 0.124 0.032 0.036 0.050 BSC 0.031 0.039 0.025 BSC 0.197 0.630 0.197 0.630 -T- 0.150 T B P DIM A B C D G H K N P 2X 0.200 -F- N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K K J H G F E D C B A G 255X K D 0.300 S T E 0.150 S S F H S T C Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature of the BGA Package 24 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.7 System Design Information This section provides electrical and thermal design recommendations for successful application of the 604. 1.7.1 PLL Configuration The SYSCLK input determines the external bus frequency at which the 604 will operate. The internal PLL can be configured to provide an internal (processor core) frequency that is a multiple of the external bus clock frequency. The PLL is configured by the PLL_CFG0-PLL_CFG3 signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU frequency of operation as shown in Table 12. Table 12. PLL Configuration Bus, CPU and VCO Frequencies PLL_CFG0 to PLL_CFG3 CPU/ SYSCLK Ratio 1:1 2:1 2:1 3:1 3:1 1.5:1 1:5:1 Bus 16.6 MHz Bus 20 MHz Bus 25 MHz Bus 33.3 MHz Bus 40 MHz Bus 50 MHz Bus 60 MHz Bus 66.6 MHz 0001 0100 0101 1000 1001 1100 1101 0011 -- -- -- -- 50 (200) -- -- -- -- 60 (240) -- -- 50 (200) -- 75 (300) -- -- 66.6 (266) 100 (200) -- -- 80 (320) 120 (240) 50 (200) 100 (200) -- 150 (300) 60 (240) 120 (240) -- -- 66.6 (266) 133 (266) -- -- -- 50 (200) PLL Bypass -- 60 (240) -- 75 (300) 90 (180) 90 (360) 100 (200) Notes: 1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not useful, not supported, or not tested for by the 604. VCO frequencies (shown in parenthesis in Table 12) should not fall below 180 MHz, and should not exceed 360 MHz. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, and the bus is set for 1:1 mode operation. The PLL-bypass mode is for test purposes only, and is not intended for functional use. 3. PLL_CFG0-PLL_CFG1 select the CPU-to-bus ratio (1:1,1.5:1, 2:1, 3:1), PLL_CFG2-PLL_CFG3 select the CPU-to-PLL multiplier (x2, x4). 604 Hardware Specifications Preliminary/Subject to Change without Notice 25 1.7.2 PLL Power Supply Filtering The AVDD power signal is provided on the 604 to provide power to the clock generation phase-lock loop. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered using a circuit similar to the one shown in Figure 16. Note that the capacitors should be placed as close as possible to the AVDD input signal. 10 OHMS VDD 10 uF .1 uF AVDD GND Figure 16. PLL Power Supply Filter Circuit 1.7.3 Decoupling Recommendations The 604 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the 604 system, and the 604 itself requires a clean, tightly regulated source of power. Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low ESR (effective series resistance) rating at each Vdd and OVdd pin of the 604. These capacitors should range in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd pin. Surface-mount tantalum or ceramic devices are preferred. It is also recommended that these decoupling capacitors receive their power from Vdd and GND power planes in the PCB, utilizing short traces to minimize inductance in the traces. Power and ground connections must be made to all external Vdd and GND pins of the 604. 1.7.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) pins must remain unconnected. 26 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.8 Thermal Management Information This section provides thermal management information for the C4-CQFP and the BGA packages. Proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, airflow and the thermal interface material. Heat sinks are typically attached to a chip package by means of a spring clip to holes in the printed-circuit board; see Figure 17. Heat Sink Thermal Interface Material Die Heat Sink Clip Printed-Circuit Board Figure 17. C4-CQFP and BGA Exploded Cross-Sectional View with Heat Sink The board designer can choose between several types of heat sinks to place on the 604. There are several commercially-available heat sinks for the 604 provided by the following vendors: Thermalloy 2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731 214-243-4321 International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 818-842-7277 Aavid Engineering One Kool Path Laconic, NH 03247-0440 Wakefield Engineering 60 Audubon Rd. Wakefield, MA 01880 603-528-3400 617-245-5900 Ultimately, the final selection of an appropriate heat sink for the 604 depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 604 Hardware Specifications Preliminary/Subject to Change without Notice 27 1.8.1 Internal Package Conduction Resistance For the exposed-die packaging technology, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case thermal resistance The die junction-to-lead thermal resistance These parameters are shown in Table 13. Table 13. Package Thermal Resistance Thermal Metric Junction-to-case thermal resistance Junction-to-lead (ball) thermal resistance C4-CQFP 0.03 C/W 18.0 C/W BGA 0.03 C/W 2.2 C/W Figure 18 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Primary Heat Transfer Path Heat Sink Silicon C4 Thermal Interface Material Chip Junction Underfill Package Substrate Package Leads/Ball Printed-Circuit Board Internal Resistance External Resistance Radiation Convection Secondary Heat Transfer Path (Note the internal versus external package resistance) Figure 18. C4 Package with Heat Sink Mounted to a Printed-Circuit Board Heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. The following section provides a thermal management example for the 604 using one of the commercially available heat-sinks. 28 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.8.2 Thermal Management Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (Rjc +Ra + Rsa) * Q Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the system cabinet Rjc is the die-junction-to-case (top of die) thermal resistance of the device Ra is the thermal resistance of the thermal interface material (thermal grease or thermal compound) Rsa is the heat sink-to-ambient thermal resistance Q is the power dissipated by the device Typical die-junction temperatures (Tj) should be maintained less than 105 C. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. A computer cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. The thermal resistance of the interface material (Ra) is typically about 1 C/W. Assuming a Ta of 30 C, a Tr of 5 C, and a power dissipation (Q) of 18 watts, the following expression for Tj is obtained: Junction temperature: Tj = 30 C + 5 C + (0.03 C/W +1.0 C/W + Rsa) * 18 W For a Thermalloy heat sink #2333B, the heatsink-to-ambient thermal resistance (Rsa) versus airflow velocity is shown in Figure 19. 10 Heat Sink Thermal Resistance (C/W) 8 Thermalloy #2333 Pin-fin Heat Sink 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 Airflow Velocity (m/s) Airflow Velocity (m/s) Figure 19. Thermalloy #2333B Pin-Fin Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity 604 Hardware Specifications Preliminary/Subject to Change without Notice 29 Assuming an air velocity of 1 m/s, we have an effective Rsa of 3 C/W, thus Tj = 30C + 5C + (0.03 C/W +1.0 C/W + 3 C/W) * 18 W, resulting in a junction temperature of approximately 107 C which is more than the maximum operating temperature of the part. To ensure maximum reliability, it is desirable to operate the 604 well within its operating temperature range. Thus, to keep an 18-watts 604 within its proper operating range, an air velocity greater than 1 m/s should be used with the Thermalloy #2333B pin-fin heat sink. Other heat sinks offered by Thermalloy, Aavid, Wakefield, and IERC offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. It is necessary to perform an analysis as done above to select the desired heat sink. Though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-ofmerit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. These factors might include airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air temperature rise, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. 1.9 Ordering Information This section provides the part numbering nomenclature for the 604. Note that the individual part numbers correspond to a specific combination of 604 internal/bus frequencies, which must be observed to ensure proper operation of the device. For available frequency combinations, contact your local Motorola or IBM sales office. In addition to the processor frequency and bus ratio, the part numbering scheme also consists of a part modifier. The part modifier allows for the availability of future enhanced parts (that is, lower voltage, lower power, higher performance, etc.). Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. 30 Preliminary/Subject to Change without Notice 604 Hardware Specifications 1.9.1 Motorola Part Number Key Figure 20 provides the Motorola part numbering nomenclature for the 604. MPC 604 X XX XXX X X Revision Level (Contact Local Motorola Sales Office) Product Code Part Identifier Part Modifier (A = Alpha--Original Production Design) Bus Divider (Contact Local Motorola Sales Office for Available Bus Ratios) Processor Speed Package (FX = C4-CQFP RX = BGA) Figure 20. Motorola Part Number Key 1.9.2 IBM Part Number Key Figure 21 provides the IBM part numbering nomenclature for the 604. PPC 604 XX X X XXX X Product Code Part Identifier Part Modifier (Not Applicable for Original Production Design) Bus Divider (Contact Local IBM Sales Office for Available Bus Ratios) Processor Speed Revision Level (Contact Local IBM Sales Office) Package (F = C4-CQFP, B = BGA) Figure 21. IBM Part Number Key 604 Hardware Specifications Preliminary/Subject to Change without Notice 31 Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 604 microprocessor embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this document and/or any of the products as described herein without further notice. NOTHING IN THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals," must be validated for each customer application by customer's technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. IBM, the IBM logo, and IBM Microelectronics are registered trademarks of International Business Machines Corporation. The PowerPC name, the PowerPC logotype, and PowerPC 604 are trademarks of International Business Machines Corporation, used under license therefrom. International Business Machines Corporation is an Equal Opportunity/Affirmative Action Employer. International Business Machines Corporation: IBM Microelectronics Division, 1580 Route 52, Bldg. 504, Hopewell Junction, NY 12533-6531; Tel. (800) PowerPC World Wide Web Address: http://www.chips.ibm.com/products/ppc http://www.ibm.com Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036; Tel.: 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F SeibuButsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan; Tel.: 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong; Tel.: 852-26629298 Technical Information: Motorola Inc. SPS Customer Support Center; (800) 521-6274. Document Comments: FAX (512) 891-2638, Attn: RISC Applications Engineering. |
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